US 12,218,783 B2
Integrated circuit with galvanic isolation
Andrea Morici, Padua (IT); and Thomas Ferianz, Bodensdorf (AT)
Assigned to Infineon Technologies Austria AG, Villach (AT)
Filed by Infineon Technologies Austria AG, Villach (AT)
Filed on Oct. 13, 2022, as Appl. No. 17/964,959.
Claims priority of application No. 21203375 (EP), filed on Oct. 19, 2021.
Prior Publication US 2023/0117387 A1, Apr. 20, 2023
Int. Cl. H02M 3/335 (2006.01); H04L 25/02 (2006.01)
CPC H04L 25/0266 (2013.01) 13 Claims
OG exemplary drawing
 
1. An integrated circuit comprising:
a galvanic insulation barrier including a first isolation element operative to separate a first isolation domain from a second isolation domain;
a first channel operative to transmit—in a first mode of operation and across the first isolation element—a first logic signal from a first input in the first isolation domain to a first output in the second isolation domain and further operative to transmit—in a second mode of operation and across the first isolation element—a first serial data stream from the first input to a first logic circuit in the second isolation domain;
a second channel operative to transmit—in the first mode of operation and across a second isolation element of the galvanic insulation barrier—a second logic signal from a second input to a second output and further operative to direct—in the second mode of operation—a clock signal received at the second input to the first logic circuit; and
wherein the first logic circuit is operative to receive—in the second mode of operation—the first serial data stream and to store configuration information included in the first serial data stream in a first memory.