US 12,218,752 B2
Communication device, processor, communication method, and computer program product
Takahiro Yamaura, Kawasaki Kanagawa (JP); and Yuta Kobayashi, Tokyo (JP)
Assigned to Kabushiki Kaisha Toshiba, Tokyo (JP); and Toshiba Infrastructure Systems & Solutions Corporation, Kawasaki (JP)
Filed by KABUSHIKI KAISHA TOSHIBA, Tokyo (JP); and TOSHIBA INFRASTRUCTURE SYSTEMS & SOLUTIONS CORPORATION, Kawasaki (JP)
Filed on Aug. 30, 2021, as Appl. No. 17/446,444.
Claims priority of application No. 2021-040208 (JP), filed on Mar. 12, 2021.
Prior Publication US 2022/0294556 A1, Sep. 15, 2022
Int. Cl. H04L 1/00 (2006.01)
CPC H04L 1/0045 (2013.01) [H04L 1/0061 (2013.01)] 10 Claims
OG exemplary drawing
 
1. A communication device comprising:
communication circuitry that receives a frame;
error detection circuitry that performs an error detection process of detecting an error in the frame;
transfer circuitry that transfers the frame to frame storage of a transfer destination without waiting for completion of the error detection process; and
transfer disablement control circuitry that, when an error is detected by the error detection circuitry, disables transfer by the transfer circuitry,
wherein
when not disabling the transfer by the transfer circuitry, the transfer disablement control circuitry updates meta-information of the transferred frame, and when disabling the transfer by the transfer circuitry, the transfer disablement control circuitry does not update the meta-information of the transferred frame, and
when the meta-information is updated, the transfer disablement control circuitry notifies the transfer destination that the meta-information is updated, and when the meta-information is not updated, the transfer disablement control circuitry does not notify the transfer destination of updating of the meta-information.