an analog front-end, configured to output a first signal;

a clock & data recovery circuit, connected to the analog front-end and configured to lock the frequency of the first signal and output a frequency locking signal; and

a detection circuit, respectively connected to the analog front-end and the clock recovery circuit, and configured to detect a data rate according to the frequency locking signal and output a bandwidth signal, a bias signal, and a completion signal according to the data rate detection result;

wherein the bandwidth signal is used to adjust the bandwidth of the clock & data recovery circuit, the bias signal is used to adjust the bandwidth of the analog front-end, and the completion signal is used to control the clock & data recovery circuit to lock the phase of the first signal,

wherein the detection circuit comprises:

a first flip-flop, configured to output a second signal according to a power supply voltage signal, the first signal, and the frequency locking signal;

a first logic gate, configured to output a third signal according to the second signal and an inverted signal;

a timing circuit, configured to output a fourth signal according to the third signal;

a second flip-flop, configured to output the completion signal according to the power supply voltage signal, the fourth signal, and the second signal;

an inverter, configured to output the inverted signal according to the completion signal;

a second logic gate, configured to output a clock count signal according to the first signal, the second signal, and the inverted signal; and

a counter, configured to output a count value according to the clock count signal and the second signal, the count value being used to look up a table to obtain parameters of the bandwidth signal and the bias signal.