US 12,218,694 B2
Bit pattern sequence compressor
Jeff L. Otto, Moscow, ID (US)
Assigned to Schweitzer Engineering Laboratories, inc., Pullman, WA (US)
Filed by Schweitzer Engineering Laboratories, Inc., Pullman, WA (US)
Filed on Apr. 5, 2023, as Appl. No. 18/295,915.
Prior Publication US 2024/0340024 A1, Oct. 10, 2024
Int. Cl. H03M 7/30 (2006.01); H01H 71/02 (2006.01); H03K 17/16 (2006.01)
CPC H03M 7/30 (2013.01) [H01H 71/0207 (2013.01); H03K 17/16 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method, comprising:
receiving a first bit pattern associated with a first multi-node device;
receiving a second bit pattern associated with a second multi-node device;
in response to determining that a logical intersection of the first bit pattern and the second bit pattern is greater than zero, compressing the first bit pattern and the second bit pattern via a logical union operation to generate a third bit pattern; and
outputting the third bit pattern, the third bit pattern indicating that the first multi-node device and the second multi-node device are electrically coupled.