US 12,218,690 B2
Apparatus for transmitting data in interleave division multiple access (IDMA) system
Ryota Kimura, Tokyo (JP); and Yifu Tang, Kanagawa (JP)
Assigned to SONY GROUP CORPORATION, Tokyo (JP)
Filed by SONY GROUP CORPORATION, Tokyo (JP)
Filed on Jun. 2, 2023, as Appl. No. 18/328,347.
Application 18/328,347 is a continuation of application No. 17/508,177, filed on Oct. 22, 2021, granted, now 11,695,432.
Application 17/508,177 is a continuation of application No. 16/898,779, filed on Jun. 11, 2020, granted, now 11,171,669, issued on Nov. 9, 2021.
Application 16/898,779 is a continuation of application No. 16/250,097, filed on Jan. 17, 2019, granted, now 10,771,093, issued on Sep. 8, 2020.
Application 16/250,097 is a continuation of application No. 15/519,862, granted, now 10,224,965, issued on Mar. 5, 2019, previously published as PCT/JP2015/070650, filed on Jul. 21, 2015.
Claims priority of application No. 2014-218184 (JP), filed on Oct. 27, 2014.
Prior Publication US 2023/0318630 A1, Oct. 5, 2023
Int. Cl. H03M 13/27 (2006.01); H04L 1/00 (2006.01)
CPC H03M 13/2792 (2013.01) [H03M 13/2778 (2013.01); H03M 13/2789 (2013.01); H04L 1/00 (2013.01); H04L 1/0058 (2013.01); H04L 1/0071 (2013.01)] 18 Claims
OG exemplary drawing
 
18. A method, comprising:
acquiring a bit sequence; and
generating an information block by de-interleave of the acquired bit sequence based on a de-interleaver, wherein
the de-interleaver corresponds to an interleaver unique to a user,
the de-interleave of the acquired bit sequence is by de-interleave of each of more than two partial sequences obtained from the acquired bit sequence,
the information block is non-decoded for error correction,
a length of each of the more than two partial sequences is a power of two, and
the bit sequence is divided into the more than two partial sequences in a specific order.