US 12,218,675 B2
Digitally augmented analog phase locked loop with accurate bandwidth
Henrik Sjöland, Lund (SE); and Razvan-Cristian Marin, Lund (SE)
Assigned to TELEFONAKTIEBOLAGET LM ERICSSON (PUBL), Stockholm (SE)
Appl. No. 18/023,585
Filed by Telefonaktiebolaget LM Ericsson (publ), Stockholm (SE)
PCT Filed Oct. 9, 2020, PCT No. PCT/EP2020/078369
§ 371(c)(1), (2) Date Feb. 27, 2023,
PCT Pub. No. WO2022/073617, PCT Pub. Date Apr. 14, 2022.
Prior Publication US 2023/0318607 A1, Oct. 5, 2023
Int. Cl. H03L 7/089 (2006.01); H03L 7/093 (2006.01); H03L 7/197 (2006.01)
CPC H03L 7/089 (2013.01) [H03L 7/093 (2013.01); H03L 7/1974 (2013.01)] 18 Claims
OG exemplary drawing
 
8. A digitally augmented analog Phase Locked Loop (PLL), comprising:
an analog PLL comprising;
a Phase Frequency Detector (PFD) configured to compare a PLL feedback signal to a reference frequency input signal and output charge-up or charge-down pulses having a length proportional to a phase error between the PLL feedback signal and reference input signal;
a Charge Pump (CP) configured to generate a positive or negative CP current in response to the length of the charge-up or charge-down pulses, respectively;
a loop filter (LF) configured to accumulate or dissipate charge on a capacitor in response to the positive or negative CP current and to output a responsive control voltage;
a Voltage Controlled Oscillator (VCO) configured to generate a periodic output signal having a frequency determined by the control voltage; and
a frequency divider (DIV) configured to divide the periodic output signal by an integer or fractional amount to generate the PLL feedback signal; and
a Time to Digital Converter (TDC) receiving the charge-up and charge-down pulses and configured to output a digital value indicating a duration of the pulses;
a digital LF calibration circuit (CAL) configured to control a value of one or both of a resistor and a capacitor in the LF so as to achieve a predetermined Resistance*Capacitance (RC) product; and
a Digital Control circuit configured to;
calibrate the LF to have the predetermined RC product; and
bandwidth characterize the analog PLL, based on the predetermined RC product, to yield a desired bandwidth.