US 12,218,674 B2
Signal generating circuit and signal generating method
Chih-Yuan Yeh, Hsinchu (TW)
Assigned to REALTEK SEMICONDUCTOR CORP., Hsinchu (TW)
Filed by REALTEK SEMICONDUCTOR CORP., Hsinchu (TW)
Filed on Jul. 24, 2023, as Appl. No. 18/225,463.
Claims priority of application No. 111127845 (TW), filed on Jul. 25, 2022.
Prior Publication US 2024/0030924 A1, Jan. 25, 2024
Int. Cl. H03L 7/07 (2006.01); H03K 3/037 (2006.01); H03K 5/00 (2006.01)
CPC H03L 7/07 (2013.01) [H03K 3/037 (2013.01); H03K 5/00006 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A signal generating circuit configured for outputting a plurality of full-cycle signals within a signal duration of a beacon signal, the signal generating circuit comprising:
a first synchronization circuit configured to receive the beacon signal and a clock signal and to synchronize the beacon signal and a first signal edge of the clock signal so as to generate a first synchronization signal;
a frequency dividing circuit configured to receive the clock signal and to perform a frequency division operation on the clock signal and generate a frequency division signal;
a second synchronization circuit configured to receive the first synchronization signal and the frequency division signal and to synchronize the first synchronization signal and a second signal edge of the frequency division signal so as to generate a second synchronization signal; and
a synthesis circuit configured to receive the second synchronization signal and the frequency division signal and to perform an AND operation on the second synchronization and the frequency division signal so as to output the full-cycle signals.