US 12,218,673 B2
Comparator circuit, method for correcting mismatch and memory
Kai Tian, Hefei (CN); and Ling Zhu, Hefei (CN)
Assigned to CHANGXIN MEMORY TECHNOLOGIES, INC., Hefei (CN)
Filed by CHANGXIN MEMORY TECHNOLOGIES, INC., Hefei (CN)
Filed on Aug. 27, 2022, as Appl. No. 17/822,775.
Application 17/822,775 is a continuation of application No. PCT/CN2022/093571, filed on May 18, 2022.
Claims priority of application No. 202210294447.9 (CN), filed on Mar. 23, 2022.
Prior Publication US 2023/0327656 A1, Oct. 12, 2023
Int. Cl. G11C 21/00 (2006.01); G11C 11/4093 (2006.01); H03K 5/24 (2006.01)
CPC H03K 5/249 (2013.01) [G11C 11/4093 (2013.01)] 18 Claims
OG exemplary drawing
 
1. A comparator circuit comprising:
a first transistor, wherein a terminal of the first transistor is coupled to a first node, another terminal of the first transistor is coupled to a first control node, and a gate of the first transistor is configured to receive a first control signal;
a second transistor, wherein a terminal of the second transistor is coupled to the first node, another terminal of the second transistor is coupled to a second control node, and a gate of the second transistor is configured to receive a second control signal;
wherein a transistor doping type of the first transistor is the same with a transistor doping type of the second transistor;
a load circuit, wherein a terminal of the load circuit is coupled to a second node, and another terminal of the load circuit is coupled to the first control node and the second control node, the load circuit is configured to adjust a level of the second control node based on a level of the first control node, or adjust the level of the first control node based on the level of the second control node, and the adjusted node in the first control node and the second control node is configured to output an output signal;
wherein the first node is configured to receive a high level and the second node is configured to receive a low level, or the first node is configured to receive the low level and the second node is configured to receive the high level;
a first adjustment circuit, wherein a terminal of the first adjustment circuit is coupled to the first node, another terminal of the first adjustment circuit is coupled to the first control node, and the first adjustment circuit is configured to adjust, according to a first adjustment signal, a node potential of the first control node, after the first transistor becomes conductive based on the first control signal; and
a second adjustment circuit, wherein a terminal of the second adjustment circuit is coupled to the first node, another terminal of the second adjustment circuit is coupled to the second control node, and the second adjustment circuit is configured to adjust, according to a second adjustment signal, a node potential of the second control node, after the second transistor becomes conductive based on the second control signal;
wherein the first adjustment signal and the second adjustment signal are configured to adjust a mismatch between the first transistor and the second transistor;
wherein the comparator circuit further comprises:
a calibration control circuit, wherein the calibration control circuit is configured to provide the first adjustment signal and the second adjustment signal;
wherein the calibration control circuit comprises:
a clock sub-circuit, configured to receive a calibration enable signal, and generate a calibration clock based on the calibration enable signal, wherein the calibration enable signal is provided in a calibration phase;
a first calibration sub-circuit, wherein the first calibration sub-circuit is coupled to the clock sub-circuit, the first calibration sub-circuit initially sets the first adjustment signal to a maximum value and the second adjustment signal to a minimum value, provides the first adjustment signal and the second adjustment signal, and gradually decreases the first adjustment signal and increases the second adjustment signal based on the calibration clock;
a judgment sub-circuit, configured to receive an output signal corresponding to different first adjustment signals and second adjustment signals, and obtain a first adjustment signal and a second adjustment signal corresponding to a first time point at which a potential inversion of the output signal occurs; and
a storage sub-circuit, wherein the storage sub-circuit is coupled to the judgment sub-circuit, the storage sub-circuit is configured to obtain the first adjustment signal and the second adjustment signal corresponding to the first time point, and provide the first adjustment signal and the second adjustment signal corresponding to the first time point in a working phase.