| CPC H03K 5/14 (2013.01) [H03K 5/00006 (2013.01); H03L 7/0807 (2013.01)] | 20 Claims |

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1. An apparatus, comprising:
a frequency multiplier having a frequency multiplier input, a frequency multiplier output, and a delay calibration input, the frequency multiplier having a first delay circuit having a delay control input coupled to the delay calibration input; and
an error detection circuit having an input and a detection output, the input of the error detection circuit coupled to the frequency multiplier output, and the detection output coupled to the delay calibration input, the error detection circuit including a second delay circuit coupled between the input and detection output.
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