an input logic circuit including a first inverter having a first input connected to a data bit and a first output, and a first clocked complementary metal-oxide semiconductor (C2MOS) circuit having a second input connected to the first output, a third input connected to a clock signal, and a clock bar signal output;

a first latch including a second C2MOS circuit having a data bit input connected to the data bit input of the input logic circuit, the clock signal, and the clock bar signal, a third C2MOS circuit, and a second inverter including an input terminal connected with an output terminal of the second C2MOS circuit and an output terminal of the third C2MOS circuit and an output terminal connected with an input terminal of the third C2MOS circuit;

a second latch including a fourth C2MOS circuit receiving the input data bit, the clock signal, and the clock bar signal, a fifth C2MOS circuit, and a third inverter including an input terminal connected with an output terminal of the fourth C2MOS circuit and an output terminal of the fifth C2MOS circuit and an output terminal connected with an input terminal of the fifth C2MOS circuit; and

an output multiplexer configured to output an output data bit by inverting a signal which is based on at least one of an output signal of a node between positive-channel metal-oxide semiconductor (PMOS) transistors of the second C2MOS circuit, an output signal of a node between negative-channel metal-oxide semiconductor (NMOS) transistors of the second C2MOS circuit, an output signal of a node between PMOS transistors of the fourth C2MOS circuit, and an output signal of a node between NMOS transistors of the fourth C2MOS circuit.