US 12,218,666 B1
Application specific integrated circuit accelerators
Michial Allen Gunter, San Francisco, CA (US); Charles Henry Leichner, IV, Palo Alto, CA (US); and Tammo Spalink, Mountain View, CA (US)
Assigned to Google LLC, Mountain View, CA (US)
Filed by Google LLC, Mountain View, CA (US)
Filed on Apr. 11, 2023, as Appl. No. 18/133,413.
Application 18/133,413 is a continuation of application No. 17/397,465, filed on Aug. 9, 2021, granted, now 11,652,484.
Application 17/397,465 is a continuation of application No. 16/827,409, filed on Mar. 23, 2020, granted, now 11,088,694, issued on Aug. 10, 2021.
Application 16/827,409 is a continuation of application No. 16/042,839, filed on Jul. 23, 2018, granted, now 10,790,828, issued on Sep. 29, 2020.
Claims priority of provisional application 62/535,652, filed on Jul. 21, 2017.
This patent is subject to a terminal disclaimer.
Int. Cl. H03K 19/17736 (2020.01); G06F 15/80 (2006.01); G06N 3/04 (2023.01); G06N 3/063 (2023.01); G06N 3/082 (2023.01); H03K 19/0175 (2006.01); G06F 15/76 (2006.01)
CPC H03K 19/17744 (2013.01) [G06F 15/8046 (2013.01); G06F 15/8053 (2013.01); G06N 3/04 (2013.01); G06N 3/063 (2013.01); G06N 3/082 (2013.01); H03K 19/017509 (2013.01); H03K 19/017545 (2013.01); H03K 19/017581 (2013.01); H03K 19/1774 (2013.01); G06F 2015/763 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An integrated circuit, comprising:
a systolic array of cells arranged in a plurality of subarrays of cells, wherein:
each cell comprises circuitry for performing an arithmetic computation;
the plurality of subarrays of cells is arranged as a grid extending along a first direction and a second direction;
a plurality of memory circuits, wherein each memory circuit of the plurality of memory circuits is arranged adjacent to a different respective subarray of cells of the plurality of subarrays of cells; and
a vector processing unit, wherein a first subset of the plurality of subarrays of cells is arranged in a first section on a first side of the vector processing unit, and a second subset of the plurality of subarrays of cells is arranged in a second section on a second side of the vector processing unit that is opposite to the first side of the vector processing unit,
the integrated circuit operable to:
transfer a first data set along the first direction to a first subarray of cells of the plurality of subarrays of cells;
transfer a first set of control instructions along the second direction to the first subarray of cells;
perform, by the first subarray of cells and in accordance with the first set of control instructions, the arithmetic computation based on the first data set to obtain a second data set; and
transfer the second data set along the first direction from the first subarray of cells.