US 12,218,665 B2
Managing data transfers in semiconductor devices by separating circuits for lower-speed-type data and higher-speed-type data
Yi-Fan Chang, Hsinchu (TW); Su-Chueh Lo, Hsinchu (TW); and Jeng-Kuan Lin, Zhubei (TW)
Assigned to Macronix International Co., Ltd., Hsinchu (TW)
Filed by Macronix International Co., Ltd., Hsinchu (TW)
Filed on Mar. 10, 2023, as Appl. No. 18/181,983.
Prior Publication US 2024/0305298 A1, Sep. 12, 2024
Int. Cl. G06F 12/00 (2006.01); G06F 3/06 (2006.01); G11C 7/10 (2006.01); H03K 3/037 (2006.01); H03K 19/00 (2006.01); H03K 19/0185 (2006.01)
CPC H03K 19/018521 (2013.01) [G06F 3/0604 (2013.01); G06F 3/0656 (2013.01); G06F 3/0679 (2013.01); G11C 7/10 (2013.01); H03K 3/037 (2013.01); H03K 19/0005 (2013.01)] 21 Claims
OG exemplary drawing
 
1. An integrated circuit, comprising:
a first interface configured to receive higher-speed-type data at a first clock frequency;
a second interface configured to receive lower-speed-type data at a second clock frequency that is same as the first clock frequency;
a first logic circuit coupled to the first interface;
a second logic circuit coupled to the second interface; and
a driving circuit separately coupled to the first logic circuit and the second logic circuit,
wherein the driving circuit is configured to output i) data corresponding to the higher-speed-type data if the first interface receives the higher-speed-type data, and ii) data corresponding to the lower-speed-type data if the second interface receives the lower-speed-type data, and
wherein the first interface, the first logic circuit, and the driving circuit are arranged to form a first data path for transferring the higher-speed-type data with a first speed, and wherein the second interface, the second logic circuit, and the driving circuit are arranged to form a second data path for transferring the lower-speed-type data with a second speed, the first speed being higher the second speed.