US 12,218,662 B1
Line driver with high over-voltage protection
Tigran Petrosyan, Yerevan (AM); Arshavir Matevosyan, Glendale, CA (US); Davit Vanetsyan, Yerevan (AM); Davit Petrosyan, Oakville (CA); and Ashot Muradyan, Yerevan (AM)
Assigned to Synopsys, Inc., Sunnyvale, CA (US)
Filed by Synopsys, Inc., Sunnyvale, CA (US)
Filed on Oct. 19, 2022, as Appl. No. 17/969,161.
Claims priority of provisional application 63/257,485, filed on Oct. 19, 2021.
Int. Cl. H03K 17/687 (2006.01)
CPC H03K 17/6874 (2013.01) 9 Claims
OG exemplary drawing
 
1. A line driver circuit, comprising:
a plurality of cascaded PMOS transistors, wherein a first PMOS transistor receives an output voltage of a first voltage level converter, a second PMOS transistor receives a first reference voltage, a third PMOS transistor and a fourth PMOS transistor, wherein a gate terminal of the third PMOS transistor and a gate terminal of the fourth PMOS transistor are connected to a first node receiving an output voltage of a second voltage level converter, wherein a source terminal of the first PMOS transistor receives a supply voltage, and wherein a drain terminal of the fourth PMOS transistor is coupled to an output terminal of the line driver circuit; and
a plurality of cascaded NMOS transistors, wherein a first NMOS transistor receives an input signal, a second NMOS transistor receives a second reference voltage, a third NMOS transistor and a fourth NMOS transistor, wherein a gate terminal of the third NMOS transistor and a gate terminal of the fourth NMOS transistor are connected to a second node receiving an output voltage of a third voltage level converter, wherein the first NMOS transistor receives a ground potential, wherein a drain terminal of the fourth NMOS transistor is coupled to the output terminal of the line driver circuit, and wherein the first, second and third voltage converters receive the input signal.