| CPC H02M 3/33569 (2013.01) [H02M 1/44 (2013.01)] | 17 Claims |
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14. A voltage converter, comprising:
a transformer having a primary winding and a secondary winding, the primary winding having first and second winding terminals;
a switch network having a first, second, third, fourth, fifth, and sixth switch network terminals, the first switch network terminal coupled to the first winding terminal, and the second switch network terminal coupled to the second winding terminal;
a first field-effect transistor (FET) having a first gate, first drain, and a first source, the first drain coupled to the third switch network terminal;
a second FET having a second gate, a second drain, and a second source, the second drain coupled to the fourth switch network terminal;
a third FET having a third gate, a third drain, a third source, the third drain coupled to the fifth switch network terminal; and
a fourth FET having a fourth gate, a fourth drain, and a fourth source, the fourth drain coupled to the sixth switch network terminal, and wherein the switch network comprises:
a fifth FET having a fifth gate, a fifth source, and a fifth drain, the fifth source coupled to the first drain;
a sixth FET having a sixth gate, a sixth source, and a sixth drain, the sixth source coupled to the second drain, the sixth gate coupled to the fifth drain, and the sixth drain coupled to the fifth gate;
a seventh FET having a seventh gate, a seventh source, and a seventh drain, the seventh drain coupled to the fifth drain and the seventh source coupled to the third drain; and
an eighth FET having an eighth gate, an eighth source, and an eighth drain, the eighth drain coupled to the sixth drain and to the seventh gate, the eighth gate coupled to the seventh drain, and the eighth source coupled to the fourth drain;
wherein during a first time period, responsive to receiving a first control signal at the first gate, receiving a second control signal at the second gate, receiving a third control signal at the third gate, and receiving a fourth control signal at the fourth gate, the second FET, the third FET, the sixth FET, and the seventh FET are configured to be on and the first FET, the fourth FET, the fifth FET, and the eighth FET are configured to be off; and
wherein during a second time period, responsive to receiving a fifth control signal at the first gate, receiving a sixth control signal at the second gate, receiving a seventh control signal at the third gate, and receiving an eighth control signal at the fourth gate, the second FET, the third FET, the sixth FET, and the seventh FET are configured to be off and the first FET, the fourth FET, the fifth FET, and the eighth FET are configured to be on.
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