US 12,218,586 B2
Charge adjustment techniques for switched capacitor power converter
Aichen Low, Cambridge, MA (US); David M. Giuliano, Bedford, NH (US); Gregory Szczeszynski, Nashua, NH (US); Jeff Summit, Jefferson, MA (US); and Oscar Blyde, Melrose, NJ (US)
Assigned to pSemi Corporation, San Diego, CA (US)
Filed by pSemi Corporation, San Diego, CA (US)
Filed on Mar. 15, 2024, as Appl. No. 18/606,285.
Application 18/606,285 is a continuation of application No. 18/049,302, filed on Oct. 25, 2022, granted, now 11,955,885.
Application 18/049,302 is a continuation of application No. 17/239,533, filed on Apr. 23, 2021, granted, now 11,522,445, issued on Dec. 5, 2022.
Application 17/239,533 is a continuation of application No. 17/079,379, filed on Oct. 23, 2020, granted, now 11,038,418, issued on Jun. 15, 2021.
Application 17/079,379 is a continuation of application No. 16/451,616, filed on Jun. 25, 2019, granted, now 10,985,651, issued on Apr. 20, 2021.
Application 16/451,616 is a continuation of application No. 14/899,887, granted, now 10,333,392, issued on Jun. 25, 2019, previously published as PCT/US2014/024143, filed on Mar. 12, 2014.
Application 14/899,887 is a continuation of application No. 13/839,315, filed on Mar. 15, 2013, granted, now 9,203,299, issued on Dec. 1, 2015.
Prior Publication US 2024/0372466 A1, Nov. 7, 2024
Int. Cl. H02M 3/07 (2006.01); H02M 1/00 (2006.01)
CPC H02M 3/07 (2013.01) [H02M 3/073 (2013.01); H02M 1/0003 (2021.05); H02M 3/075 (2021.05)] 22 Claims
OG exemplary drawing
 
1. An integrated circuit, comprising:
a switched capacitor circuit having a set of switches configured to form at least a portion of a step-down voltage converter, wherein the set of switches is configured to couple to a set of capacitors arranged to form a configuration such that at least some switches in the set of switches operate in a manner to form an electrical connection of at least some of the capacitors to respective alternate voltages in successive stages of operation of the step-down voltage converter;
a current-limited switch coupled to a source and the switched capacitor circuit; and
a sense circuit connected to the current-limited switch and configured to detect an input current exceeding a current limit level,
wherein the current-limited switch is configured to suppress an electrical input to the switched capacitor circuit upon the sense circuit detecting the input current exceeding the current limit level.