US 12,218,579 B2
Semiconductor device
Hideyuki Tajima, Tokyo (JP)
Assigned to Renesas Electronics Corporation, Tokyo (JP)
Filed by Renesas Electronics Corporation, Tokyo (JP)
Filed on Dec. 22, 2022, as Appl. No. 18/145,328.
Claims priority of application No. 2021-207824 (JP), filed on Dec. 22, 2021.
Prior Publication US 2023/0198378 A1, Jun. 22, 2023
Int. Cl. G05F 3/26 (2006.01); H02M 1/00 (2007.01); H02M 1/08 (2006.01); H02M 1/32 (2007.01); H02M 3/158 (2006.01)
CPC H02M 1/32 (2013.01) [G05F 3/262 (2013.01); H02M 1/0009 (2021.05); H02M 1/08 (2013.01); H02M 3/158 (2013.01); H02M 1/0006 (2021.05)] 7 Claims
OG exemplary drawing
 
1. A semiconductor device comprising:
a constant current generating circuit unit;
a first current mirror circuit unit having as an input current a constant current outputted by the constant current generating circuit unit, and generating a first mirror current as a mirror current;
a level shift current unit including a clamp transistor between whose drain and source the first mirror current flows and to whose base a power supply voltage of the constant current generating circuit unit is applied, and a transistor that is connected in series to the clamp transistor and through which the first mirror current flows;
a second current mirror circuit unit having as an input stage the transistor and having as an output stage a transistor through which a second mirror current obtained by replicating the first mirror current flows; and
an error absorption circuit unit having a capacitance corresponding to a parasitic capacitance of the clamp transistor connected to a terminal for outputting the second mirror current of the output-stage transistor in the second current mirror circuit unit.