US 12,218,497 B1
Optically switched circuit breaker with cascaded transistor topology
Gregory Pickrell, Rio Rancho, NM (US); Jason Christopher Neely, Albuquerque, NM (US); Lee Gill, Albuquerque, NM (US); Jacob Mueller, Albuquerque, NM (US); Luciano Andres Garcia Rodriguez, Albuquerque, NM (US); Jack David Flicker, Albuquerque, NM (US); Emily Ann Schrock, Albuquerque, NM (US); Robert Kaplar, Albuquerque, NM (US); Harold P. Hjalmarson, Albuquerque, NM (US); and Jane Lehr, Placitas, NM (US)
Assigned to National Technology & Engineering Solutions of Sandia, LLC, Albuquerque, NM (US); and UNM Rainforest Innovations, Albuquerque, NM (US)
Filed by National Technology & Engineering Solutions of Sandia, LLC, Albuquerque, NM (US)
Filed on Oct. 12, 2022, as Appl. No. 17/964,772.
Application 17/964,772 is a continuation in part of application No. 17/737,593, filed on May 5, 2022, granted, now 11,728,804.
Int. Cl. H03K 5/08 (2006.01); H02H 1/00 (2006.01); H02H 9/02 (2006.01); H02M 1/088 (2006.01); H02M 1/34 (2007.01); H03K 17/10 (2006.01); H03K 17/16 (2006.01); H03K 17/687 (2006.01); H03K 17/693 (2006.01)
CPC H02H 9/02 (2013.01) [H02H 1/0007 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A switching apparatus having a power input terminal for electric power and a load terminal for connection to a load, comprising:
a transistor switch circuit connected between the power input terminal and the load terminal; and
a switchable bypass leg connected to the power input terminal and bypassing the transistor switch circuit, the switchable bypass leg including a series-connected photoconductive semiconductor switch (PCSS);
wherein the switchable bypass leg is configured to be optically switchable by the PCSS;
wherein the transistor switch circuit comprises:
at least a first plurality of n series-connected transistors, each of said transistors having a respective source terminal, a respective drain terminal, and a respective gate terminal, wherein for n a positive integer at least 3, the first plurality of n series-connected transistors includes a first transistor herein denominated J1, a last transistor herein denominated Jn, and at least one transistor herein denominated Ji, i having respective positive integer values between 1 and n;
a terminal S connected to the J1 source terminal;
a terminal D connected to the Jn drain terminal;
a control terminal G connected to the J1 gate terminal; and
a dedicated voltage-balancing network connected between terminal S and terminal D; and
wherein the dedicated voltage-balancing network includes a number, at least two, of parallel-connected resistive legs, each parallel-connected resistive leg includes two or more series-connected resistors, and for each transistor after J1, the gate terminal connects to one of the parallel-connected resistive legs such that the parallel-connected resistive legs collectively constitute a voltage divider for dividing voltage across the n series-connected transistors.