US 12,218,256 B1
Trench MOS rectifier with termination structure
Tao Long, Shanghai (CN); Ze Rui Chen, Plano, TX (US); Pin-Hao Huang, New Taipei (TW); Bau-Shun Huang, New Taipei (TW); and Lee Spencer Riley, Lancashire (GB)
Assigned to DIODES INCORPORATED, Plano, TX (US)
Filed by Diodes Incorporated, Plano, TX (US)
Filed on Jul. 16, 2024, as Appl. No. 18/774,563.
Claims priority of application No. 202311450972.6 (CN), filed on Nov. 2, 2023.
Int. Cl. H01L 29/872 (2006.01); H01L 23/58 (2006.01); H01L 27/102 (2023.01); H01L 29/06 (2006.01); H01L 29/66 (2006.01)
CPC H01L 29/8725 (2013.01) [H01L 23/585 (2013.01); H01L 27/1021 (2013.01); H01L 29/0623 (2013.01); H01L 29/66143 (2013.01)] 7 Claims
OG exemplary drawing
 
1. A manufacturing method for a semiconductor structure, the method comprising:
forming on a substrate, at intervals in a first direction, a first trench, a second trench, and a third trench extending from a second surface towards a first surface opposite the second surface, wherein a cell region and a terminal region seen in a plan view are defined on the substrate, the first trench and the second trench being provided in the cell region, and the third trench being provided in the terminal region;
forming a first oxide layer in the first trench, forming a second oxide layer in the second trench, and forming a third oxide layer in the third trench;
forming a first semiconductor material layer in the first trench to cause the first semiconductor material layer to be surrounded by the first oxide layer to form a first trench structure, forming a second semiconductor material layer in the second trench to cause the second semiconductor material layer to be surrounded by the second oxide layer to form a second trench structure, and forming a third semiconductor material layer in the third trench to cause the third semiconductor material layer to be surrounded by the third oxide layer to form a third trench structure;
forming a mask layer on the cell region, the first trench structure, and the second trench structure;
performing a first etching process on the mask layer to form a first opening and a second opening, the first opening extending in the first direction such that at least part of the first semiconductor material layer is exposed, and the second opening extending in a second direction perpendicular to the first direction such that at least part of the second surface and the first trench structure are exposed;
after the first etching process, performing a second etching process at the second opening to form a third surface on the substrate and to cause the first trench structure and the second trench structure to at least partially protrude from the third surface of the cell region; and
forming a first doped region adjacent to the third surface exposed by the second opening, wherein when seen in a plan view, the first doped region is provided between the first trench structure and the second trench structure, and extends in the second direction.