US 12,218,253 B2
Flash memory device with three dimensional half flash structure and methods for forming the same
Yu-Chu Lin, Tainan (TW); Chi-Chung Jen, Kaohsiung (TW); Wen-Chih Chiang, Hsinchu (TW); Yi-Ling Liu, Hsinchu (TW); Huai-Jen Tung, Tainan (TW); and Keng-Ying Liao, Tainan (TW)
Assigned to Taiwan Semiconductor Manufacturing Company Limited, Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company Limited, Hsinchu (TW)
Filed on Apr. 15, 2023, as Appl. No. 18/301,220.
Application 18/301,220 is a continuation of application No. 17/191,334, filed on Mar. 3, 2021, granted, now 11,658,248.
Prior Publication US 2023/0253508 A1, Aug. 10, 2023
Int. Cl. H01L 29/788 (2006.01); H01L 21/265 (2006.01); H01L 21/28 (2006.01); H01L 29/417 (2006.01); H01L 29/423 (2006.01); H01L 29/66 (2006.01); H01L 29/78 (2006.01); H10B 41/30 (2023.01)
CPC H01L 29/7883 (2013.01) [H01L 21/26513 (2013.01); H01L 29/40114 (2019.08); H01L 29/41725 (2013.01); H01L 29/42324 (2013.01); H01L 29/66492 (2013.01); H01L 29/66825 (2013.01); H01L 29/7833 (2013.01); H10B 41/30 (2023.02)] 20 Claims
OG exemplary drawing
 
1. A memory cell, comprising:
a channel region in a substrate;
a gate structure comprising:
a control gate dielectric layer on the channel region and having a first length in a first direction;
a control gate on the control gate dielectric layer and having a second length in the first direction less than the first length; and
a second sidewall spacer on a second sidewall of the control gate and on the control gate dielectric layer;
a first contact contacting the control gate dielectric layer over the channel region, having a height greater than a height of the control gate and including an outermost sidewall opposite the control gate and over the channel region; and
an interlevel dielectric layer on opposing sides of the first contact and contacting the control gate dielectric layer at the second sidewall spacer and over the channel region.