US 12,218,249 B2
Semiconductor device comprising oxide semiconductor layer containing a c-axis aligned crystal
Shunpei Yamazaki, Setagaya (JP)
Assigned to Semiconductor Energy Laboratory Co., Ltd., Atsugi (JP)
Filed by Semiconductor Energy Laboratory Co., Ltd., Atsugi (JP)
Filed on Jul. 28, 2023, as Appl. No. 18/227,361.
Application 14/108,840 is a division of application No. 12/957,441, filed on Dec. 1, 2010, granted, now 8,624,245, issued on Jan. 7, 2014.
Application 18/227,361 is a continuation of application No. 17/741,698, filed on May 11, 2022, granted, now 11,728,437.
Application 17/741,698 is a continuation of application No. 17/110,603, filed on Dec. 3, 2020, granted, now 11,342,464, issued on May 24, 2022.
Application 17/110,603 is a continuation of application No. 16/672,978, filed on Nov. 4, 2019, granted, now 10,861,983, issued on Dec. 8, 2020.
Application 16/672,978 is a continuation of application No. 16/017,104, filed on Jun. 25, 2018, granted, now 10,505,049, issued on Dec. 10, 2019.
Application 16/017,104 is a continuation of application No. 15/665,696, filed on Aug. 1, 2017, granted, now 10,014,415, issued on Jul. 3, 2018.
Application 15/665,696 is a continuation of application No. 15/086,148, filed on Mar. 31, 2016, granted, now 9,735,284, issued on Aug. 15, 2017.
Application 15/086,148 is a continuation of application No. 14/567,282, filed on Dec. 11, 2014, granted, now 9,324,881, issued on Apr. 26, 2016.
Application 14/567,282 is a continuation of application No. 14/108,840, filed on Dec. 17, 2013, granted, now 8,927,349, issued on Jan. 6, 2015.
Claims priority of application No. 2009-276334 (JP), filed on Dec. 4, 2009.
Prior Publication US 2023/0369511 A1, Nov. 16, 2023
Int. Cl. H01L 29/786 (2006.01); H01L 27/12 (2006.01); H01L 29/04 (2006.01); H01L 29/24 (2006.01); H01L 29/66 (2006.01)
CPC H01L 29/7869 (2013.01) [H01L 27/1225 (2013.01); H01L 29/04 (2013.01); H01L 29/045 (2013.01); H01L 29/24 (2013.01); H01L 29/66969 (2013.01); H01L 29/78648 (2013.01); H01L 29/78693 (2013.01); H01L 29/78696 (2013.01)] 2 Claims
OG exemplary drawing
 
1. A semiconductor device comprising:
a first conductive layer;
a first insulating layer over the first conductive layer;
an oxide semiconductor layer including a channel formation region of a transistor, over the first insulating layer; and
a second conductive layer in contact with a top surface of the oxide semiconductor layer,
wherein the first conductive layer is configured to be a gate electrode of the transistor,
wherein the second conductive layer is configured to be a source electrode or a drain electrode of the transistor,
wherein the oxide semiconductor layer includes a first region overlapping the first conductive layer, a second region overlapping the first conductive layer and the second conductive layer, and a third region overlapping the second conductive layer,
wherein the first region includes a crystal grain whose c-axis is aligned, and
wherein the second region is closer to the first conductive layer than the first region.