US 12,218,241 B2
Semiconductor device structure with etch stop layer for reducing RC delay
Chung-Ting Ko, Kaohsiung (TW); Bo-Cyuan Lu, New Taipei (TW); Jr-Hung Li, Chupei (TW); and Chi-On Chui, Hsinchu (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed by TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed on Mar. 28, 2022, as Appl. No. 17/705,885.
Application 17/705,885 is a continuation of application No. 16/662,922, filed on Oct. 24, 2019, granted, now 11,316,047.
Application 16/662,922 is a continuation of application No. 15/646,386, filed on Jul. 11, 2017, granted, now 10,468,529, issued on Nov. 5, 2019.
Prior Publication US 2022/0223736 A1, Jul. 14, 2022
Int. Cl. H01L 21/02 (2006.01); H01L 21/768 (2006.01); H01L 23/535 (2006.01); H01L 29/04 (2006.01); H01L 29/08 (2006.01); H01L 29/165 (2006.01); H01L 29/66 (2006.01); H01L 29/78 (2006.01); H01L 21/8234 (2006.01); H01L 27/088 (2006.01); H01L 29/06 (2006.01); H01L 29/51 (2006.01)
CPC H01L 29/7851 (2013.01) [H01L 21/0217 (2013.01); H01L 21/022 (2013.01); H01L 21/02211 (2013.01); H01L 21/02247 (2013.01); H01L 21/02252 (2013.01); H01L 21/0228 (2013.01); H01L 21/76829 (2013.01); H01L 23/535 (2013.01); H01L 29/04 (2013.01); H01L 29/0847 (2013.01); H01L 29/165 (2013.01); H01L 29/66545 (2013.01); H01L 29/66795 (2013.01); H01L 29/7848 (2013.01); H01L 21/76897 (2013.01); H01L 21/823431 (2013.01); H01L 21/823468 (2013.01); H01L 21/823475 (2013.01); H01L 21/823481 (2013.01); H01L 27/0886 (2013.01); H01L 29/0649 (2013.01); H01L 29/517 (2013.01); H01L 29/6656 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor device structure, comprising:
a substrate;
a gate structure over the substrate;
a spacer element covering a first sidewall of the gate structure;
a source/drain portion in the substrate, wherein the spacer element is between the source/drain portion and the gate structure;
an etch stop layer covering the source/drain portion, wherein a topmost surface of the etch stop layer is closer to the substrate than a topmost surface of the gate structure, and the etch stop layer comprises:
a first nitride layer covering the source/drain portion and having a second sidewall, wherein the second sidewall is in direct contact with the spacer element; and
a first silicon layer covering the first nitride layer and having a third sidewall, wherein the third sidewall is in direct contact with the spacer element; and
a dielectric layer over the etch stop layer, wherein the dielectric layer has a fourth sidewall and a bottom surface, the etch stop layer is in direct contact with the bottom surface, and the spacer element is in direct contact with the fourth sidewall.