US 12,218,234 B2
Semiconductor device and method of manufacturing the same
Kengo Omori, Kyoto (JP)
Assigned to ROHM CO., LTD., Kyoto (JP)
Filed by ROHM CO., LTD., Kyoto (JP)
Filed on Aug. 2, 2023, as Appl. No. 18/364,082.
Application 14/147,614 is a division of application No. 13/590,665, filed on Aug. 21, 2012, granted, now 8,653,593, issued on Apr. 18, 2014.
Application 18/364,082 is a continuation of application No. 17/972,100, filed on Oct. 24, 2022, granted, now 11,757,033.
Application 17/972,100 is a continuation of application No. 17/337,155, filed on Jun. 2, 2021, granted, now 11,557,672, issued on Jan. 17, 2023.
Application 17/337,155 is a continuation of application No. 16/990,423, filed on Aug. 11, 2020, granted, now 11,038,050, issued on Jun. 15, 2021.
Application 16/990,423 is a continuation of application No. 16/785,074, filed on Feb. 7, 2020, granted, now 10,770,583, issued on Sep. 8, 2020.
Application 16/785,074 is a continuation of application No. 16/210,247, filed on Dec. 5, 2018, granted, now 10,593,794, issued on Mar. 17, 2020.
Application 16/210,247 is a continuation of application No. 15/880,631, filed on Jan. 26, 2018, granted, now 10,164,090, issued on Dec. 25, 2018.
Application 15/880,631 is a continuation of application No. 15/336,985, filed on Oct. 28, 2016, granted, now 9,917,185, issued on Mar. 13, 2018.
Application 15/336,985 is a continuation of application No. 14/800,992, filed on Jul. 16, 2015, granted, now 9,502,495, issued on Nov. 22, 2016.
Application 14/800,992 is a continuation of application No. 14/147,614, filed on Jan. 6, 2014, granted, now 9,117,683, issued on Aug. 25, 2015.
Claims priority of application No. 2011-183041 (JP), filed on Aug. 24, 2011; application No. 2011-211443 (JP), filed on Sep. 27, 2011; and application No. 2012-132261 (JP), filed on Jun. 11, 2012.
Prior Publication US 2023/0378344 A1, Nov. 23, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 29/78 (2006.01); H01L 21/265 (2006.01); H01L 21/8234 (2006.01); H01L 29/06 (2006.01); H01L 29/10 (2006.01); H01L 29/417 (2006.01); H01L 29/423 (2006.01); H01L 29/66 (2006.01)
CPC H01L 29/7813 (2013.01) [H01L 21/26586 (2013.01); H01L 21/823487 (2013.01); H01L 29/0615 (2013.01); H01L 29/1095 (2013.01); H01L 29/41766 (2013.01); H01L 29/4236 (2013.01); H01L 29/66727 (2013.01); H01L 29/66734 (2013.01); H01L 29/7827 (2013.01); H01L 29/0696 (2013.01); H01L 29/42376 (2013.01)] 14 Claims
OG exemplary drawing
 
1. An SiC semiconductor device comprising:
a semiconductor layer having a first surface and a second surface;
a first trench on the first surface of the semiconductor layer;
a second trench on the first surface of the semiconductor layer;
first regions of a first conductivity type provided at the first surface of the semiconductor layer, one of the first regions forming a first part of a side surface of the first trench and another of the first regions forming a first part of a side surface of the second trench;
a second region of a second conductivity type on a side of the first regions facing the second surface of the semiconductor layer, the second region forming a second part of the side surface of the first trench and a second part of the side surface of the second trench;
a contact region of the second conductivity type on a surface of the second region;
a third region of the first conductivity type below the second region, the third region forming a bottom surface of the first trench and a bottom surface of the second trench;
a plurality of insulating films each of which is on an inner surface of the first trench and on an inner surface of the second trench; and
an electrode embedded inside the insulating films in each of the first trench and the second trench, wherein
the second region includes a first portion closer to the first surface of the semiconductor layer and a second portion below the first portion, the second portion is projecting from the first portion toward the second surface of the semiconductor layer to a depth below the bottom surfaces of the first trench and the second trench,
the second portion includes a boundary portion with the third region, a part of the boundary portion being at an incline with respect to the first surface of the semiconductor layer, and
a peak of depth of the second portion is placed in a region between the first trench and the second trench, and below the contact region.