US 12,218,233 B2
High electron mobility transistor and method of manufacturing the same
Jaejoon Oh, Seongnam-si (KR); and Jongseob Kim, Seoul (KR)
Assigned to Samsung Electronics Co., Ltd., Gyeonggi-do (KR)
Filed by Samsung Electronics Co., Ltd., Suwon-si (KR)
Filed on Sep. 2, 2022, as Appl. No. 17/902,383.
Application 17/902,383 is a division of application No. 16/939,274, filed on Jul. 27, 2020, abandoned.
Claims priority of application No. 10-2020-0035803 (KR), filed on Mar. 24, 2020.
Prior Publication US 2022/0416071 A1, Dec. 29, 2022
Int. Cl. H01L 29/778 (2006.01); H01L 21/285 (2006.01); H01L 29/20 (2006.01); H01L 29/205 (2006.01); H01L 29/423 (2006.01); H01L 29/66 (2006.01)
CPC H01L 29/7786 (2013.01) [H01L 21/28587 (2013.01); H01L 29/2003 (2013.01); H01L 29/205 (2013.01); H01L 29/42316 (2013.01); H01L 29/66462 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A high electron mobility transistor comprising:
a channel layer including a first semiconductor material;
a channel supplying layer including a second semiconductor material and causing generation of a two-dimensional electron gas (2DEG) in the channel layer;
a source electrode and a drain electrode provided on both sides of the channel supplying layer and spaced apart from each other in a first direction;
a depletion forming layer provided on the channel supplying layer to form a depletion region in the 2DEG;
a gate electrode provided on a portion of the depletion forming layer; and
a current limiting layer provided to contact the gate electrode on another portion of the depletion forming layer, and configured to limit a current flow from the gate electrode to the depletion forming layer according to a voltage applied to the gate electrode,
wherein the gate electrode comprises an upper portion in contact with an upper surface of the current limiting layer and a lower portion in contact with a side surface of the current limiting layer,
wherein the depletion forming layer includes portions spaced apart from each other in a direction parallel to a length of the gate electrode, the direction parallel to the length of the gate electrode being a second direction crossing the first direction,
wherein the current limiting layer is of an integral type and extends in the direction parallel to the length of the gate electrode,
the portions of the depletion forming layer are physically separated from each other,
the portions of the depletion forming layer include a first portion spaced from a second portion, and
a sidewall of the first portion is spaced apart from and faces a sidewall of the second portion.