US 12,218,231 B2
HEMT transistor including field plate regions and manufacturing process thereof
Ferdinando Iucolano, Gravina di Catania (IT); and Alessandro Chini, Modena (IT)
Assigned to STMicroelectronics S.r.l., Agrate Brianza (IT)
Filed by STMicroelectronics S.r.l., Agrate Brianza (IT)
Filed on Dec. 9, 2020, as Appl. No. 17/116,465.
Claims priority of application No. 102019000023475 (IT), filed on Dec. 10, 2019.
Prior Publication US 2021/0175350 A1, Jun. 10, 2021
Int. Cl. H01L 29/778 (2006.01); H01L 29/20 (2006.01); H01L 29/205 (2006.01); H01L 29/40 (2006.01); H01L 29/66 (2006.01)
CPC H01L 29/7786 (2013.01) [H01L 29/2003 (2013.01); H01L 29/205 (2013.01); H01L 29/404 (2013.01); H01L 29/66462 (2013.01); H01L 29/7787 (2013.01)] 19 Claims
OG exemplary drawing
 
1. A HEMT transistor comprising:
a semiconductor body having a semiconductive heterostructure;
a gate region, of conductive material, arranged on and in contact with the semiconductor body;
a first insulating layer extending over the semiconductor body, laterally to the gate region;
a second insulating layer extending over the first insulating layer and the gate region;
a first field plate region, of conductive material, extending between the first and the second insulating layers, laterally spaced from the gate region along a first direction, wherein the second insulating layer is in contact with a top surface of the gate region and a top surface of the first field plate region; and
a second field plate region, of conductive material, extending over the second insulating layer, the second field plate region overlying the first field plate region, wherein the gate region includes a lower gate portion and an upper gate portion, the lower gate portion extending into a first opening of the first insulating layer and in contact with the semiconductor body; and
a dielectric layer extending between the first and the second insulating layers, wherein the dielectric layer has a second opening and a third opening, the gate region having an intermediate gate portion extending into the second opening, between the upper gate portion and the lower gate portion, and wherein the first field plate region has a lower plate portion extending through the third opening of the dielectric layer and in a cavity of the first insulating layer, a reduced thickness portion of the first insulating layer extending between the lower plate portion and the semiconductor body.