US 12,218,227 B2
Semiconductor structure
Shih-Hao Lin, Hsinchu (TW); Chia-Hung Chou, Hsinchu (TW); Chih-Hsuan Chen, Hsinchu (TW); Ping-En Cheng, Hsinchu (TW); Hsin-Wen Su, Yunlin County (TW); Chien-Chih Lin, Taichung (TW); and Szu-Chi Yang, Hsinchu (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on Aug. 10, 2023, as Appl. No. 18/447,932.
Application 18/447,932 is a continuation of application No. 17/332,025, filed on May 27, 2021, granted, now 11,742,416.
Prior Publication US 2023/0395703 A1, Dec. 7, 2023
Int. Cl. H01L 29/66 (2006.01); H01L 21/8234 (2006.01); H01L 29/78 (2006.01)
CPC H01L 29/6681 (2013.01) [H01L 21/823431 (2013.01); H01L 21/823468 (2013.01); H01L 29/66553 (2013.01); H01L 29/6656 (2013.01); H01L 29/7851 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor structure, comprising:
a substrate;
semiconductor layers extending in an X-direction and over the substrate, wherein the semiconductor layers are spaced apart from each other in a Z-direction;
source/drain features on opposite sides of the semiconductor layers in the X-direction;
metal oxide layers covering bottom surfaces of the semiconductor layers; and
a gate structure wrapping around the semiconductor layers and the metal oxide layers, wherein center portions of the metal oxide layers covering the bottom surfaces of the semiconductor layers are in contact with the gate structure.