US 12,218,226 B2
Methods of fabricating semiconductor devices having gate-all-around structure with inner spacer last process
Chun-Hsiung Lin, Zhubei (TW); Pei-Hsun Wang, Kaohsiung (TW); Chih-Hao Wang, Baoshan Township, Hsinchu County (TW); Kuo-Cheng Ching, Zhubei (TW); and Jui-Chien Huang, Hsinchu (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on Oct. 27, 2020, as Appl. No. 17/081,365.
Application 17/081,365 is a division of application No. 16/282,214, filed on Feb. 21, 2019, granted, now 10,825,919.
Prior Publication US 2021/0066473 A1, Mar. 4, 2021
Int. Cl. H01L 29/66 (2006.01); H01L 21/8234 (2006.01); H01L 29/06 (2006.01); H01L 29/417 (2006.01); H01L 29/78 (2006.01)
CPC H01L 29/6681 (2013.01) [H01L 21/823431 (2013.01); H01L 21/823481 (2013.01); H01L 29/0653 (2013.01); H01L 29/41791 (2013.01); H01L 29/785 (2013.01); H01L 2029/7858 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor device, comprising:
a plurality of channel layers and a source/drain structure over a fin;
a gate structure wrapping around the plurality of channel layers;
a plurality of inner spacers between the gate structure and the source/drain structure;
a doped portion between a first channel of the plurality of channel layers and the source/drain structure and between a first inner spacer and a second inner spacer of the plurality of inner spacers, wherein a doped concentration of a dopant in the doped portion is greater than a doped concentration of the dopant in the channel layers, and the dopant is carbon, germanium or a combination thereof;
a gate spacer alongside the gate structure, wherein the first inner spacer is a topmost one of the inner spacers, and the first inner spacer is interposed between the gate spacer and the doped portion and in direct contact with the both gate spacer and the gate structure; and
a doped semiconductor layer directly below the plurality of inner spacers and the source/drain structure; and
a silicon layer directly below the plurality of channel layers and over the fin, wherein a sidewall of the doped semiconductor layer is interfaced with a sidewall of the silicon layer.