US 12,218,220 B2
Manufacturing method of semiconductor structure and semiconductor structure
Shuai Guo, Hefei (CN); Mingguang Zuo, Hefei (CN); and Shijie Bai, Hefei (CN)
Assigned to CHANGXIN MEMORY TECHNOLOGIES, INC., Hefei (CN)
Filed by CHANGXIN MEMORY TECHNOLOGIES, INC., Hefei (CN)
Filed on Apr. 29, 2022, as Appl. No. 17/661,359.
Application 17/661,359 is a continuation of application No. PCT/CN2022/078671, filed on Mar. 1, 2022.
Claims priority of application No. 202210049426.0 (CN), filed on Jan. 17, 2022.
Prior Publication US 2023/0231036 A1, Jul. 20, 2023
Int. Cl. H01L 21/8234 (2006.01); H01L 29/66 (2006.01); H01L 29/786 (2006.01)
CPC H01L 29/66742 (2013.01) [H01L 21/823412 (2013.01); H01L 21/823481 (2013.01); H01L 29/78696 (2013.01)] 17 Claims
OG exemplary drawing
 
16. A semiconductor structure, comprising a substrate, a thin-film stacked structure, an epitaxial silicon pillar and a first isolation layer, wherein the thin-film stacked structure is provided on a surface of the substrate; a first hole exposing the substrate is formed in the thin-film stacked structure; the epitaxial silicon pillar is provided in the first hole; the first isolation layer is provided in a first trench; the first trench is formed by removing a part of the thin-film stacked structure and a part of the epitaxial silicon pillar along a first direction; the first trench passes through a center of the epitaxial silicon pillar and divides the epitaxial silicon pillar into a first half pillar and a second half pillar; a first channel region of a first doping type is formed in a sidewall of the first half pillar away from the first trench; a second channel region of a second doping type is formed in a sidewall of the second half pillar away from the first trench; one of the first doping type and the second doping type is an N type, and the other one is a P type; and a gate dielectric layer and a gate conductive layer are arranged on a surface of each of the first channel region and the second channel region.