US 12,218,219 B2
Spacer structure for semiconductor device
Jung-Hao Chang, Taichung (TW); Fo-Ju Lin, Keelung (TW); Fang-Wei Lee, Hsinchu (TW); Li-Te Lin, Hsinchu (TW); and Pinyen Lin, Rochester, NY (US)
Assigned to Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed on Aug. 27, 2021, as Appl. No. 17/459,788.
Prior Publication US 2023/0068619 A1, Mar. 2, 2023
Int. Cl. H01L 29/66 (2006.01); H01L 21/311 (2006.01); H01L 29/423 (2006.01); H01L 29/786 (2006.01)
CPC H01L 29/66553 (2013.01) [H01L 21/31116 (2013.01); H01L 29/42392 (2013.01); H01L 29/66742 (2013.01); H01L 29/78618 (2013.01); H01L 29/78696 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method, comprising:
forming a fin structure over a substrate, wherein the fin structure comprises first and second sacrificial layers;
forming a recess structure in a first portion of the fin structure;
selectively etching the first sacrificial layer of a second portion of the fin structure over the second sacrificial layer of the second portion of the fin structure; and
forming an inner spacer layer over the etched first sacrificial layer with the second sacrificial layer of the second portion of the fin structure being exposed.