US 12,218,218 B2
Nanostructures formed over a substrate and a gate structure wrapping around the nanostructures
Yi-Ruei Jhan, Keelung (TW); Kuo-Cheng Chiang, Zhubei (TW); and Chih-Hao Wang, Baoshan Township (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on Mar. 9, 2022, as Appl. No. 17/690,354.
Prior Publication US 2023/0290859 A1, Sep. 14, 2023
Int. Cl. H01L 29/66 (2006.01); H01L 27/088 (2006.01); H01L 29/06 (2006.01); H01L 29/08 (2006.01); H01L 29/417 (2006.01); H01L 29/423 (2006.01); H01L 29/786 (2006.01)
CPC H01L 29/66545 (2013.01) [H01L 27/088 (2013.01); H01L 29/0673 (2013.01); H01L 29/0847 (2013.01); H01L 29/41766 (2013.01); H01L 29/6653 (2013.01); H01L 29/66742 (2013.01); H01L 29/78696 (2013.01); H01L 29/42392 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method for forming a semiconductor device structure, comprising:
forming a first fin structure and a second fin structure over a substrate, wherein the first fin structure comprises a plurality of first semiconductor layers and a plurality of second semiconductor layers stacked in a vertical direction, and the second fin structure comprises a plurality of first semiconductor layers and a plurality of second semiconductor layers stacked in a vertical direction;
forming a hard mask layer over the first fin structure and the second fin structure;
patterning the hard mask layer to form a trench;
forming a gate spacer layer in the trench;
forming a dummy gate electrode layer in the trench and on the gate spacer layer;
removing the hard mask layer;
removing a portion of the first fin structure and a portion of the second fin structure to form a first S/D recess and a second S/D recess; and
forming a first source/drain (S/D) structure in the first S/D recess and a second S/D structure in the second S/D recess.