US 12,218,217 B2
Layer structure including dielectric layer, methods of manufacturing the layer structure, and electronic device including the layer structure
Yunseong Lee, Osan-si (KR); Jinseong Heo, Seoul (KR); Taehwan Moon, Suwon-si (KR); Seunggeol Nam, Suwon-si (KR); and Dukhyun Choe, Suwon-si (KR)
Assigned to Samsung Electronics Co., Ltd., Gyeonggi-do (KR)
Filed by Samsung Electronics Co., Ltd., Suwon-si (KR)
Filed on Dec. 8, 2021, as Appl. No. 17/545,442.
Claims priority of application No. 10-2021-0090490 (KR), filed on Jul. 9, 2021.
Prior Publication US 2023/0009791 A1, Jan. 12, 2023
Int. Cl. H01L 29/51 (2006.01); H10B 51/00 (2023.01); H10B 53/00 (2023.01)
CPC H01L 29/516 (2013.01) [H10B 51/00 (2023.02); H10B 53/00 (2023.02)] 26 Claims
OG exemplary drawing
 
1. A layer structure comprising:
a lower layer;
an upper layer; and
a dielectric layer between the lower layer and the upper layer, the dielectric layer comprising
a first layer,
a second layer on the first layer, the second layer including an oxide layer, and
a third layer on the second layer,
wherein one of the first layer or the third layer is a ferroelectric and a remainder of the first and third layers is an anti-ferroelectric,
wherein the oxide layer directly contacts the ferroelectric and the anti-ferroelectric, and
wherein each of the first layer and the third layer is a single layer.