US 12,218,216 B2
Method for manufacturing semiconductor devices having gate spacers with bottom portions recessed in a fin
Wei-Liang Lu, Hsinchu (TW); Chang-Yin Chen, Taipei (TW); Chih-Han Lin, Hsinchu (TW); and Chia-Yang Liao, Hsinchu (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on Aug. 9, 2023, as Appl. No. 18/232,191.
Application 18/232,191 is a division of application No. 17/244,430, filed on Apr. 29, 2021.
Claims priority of provisional application 63/055,240, filed on Jul. 22, 2020.
Prior Publication US 2023/0387245 A1, Nov. 30, 2023
Int. Cl. H01L 29/66 (2006.01); H01L 21/8234 (2006.01); H01L 21/8238 (2006.01); H01L 27/088 (2006.01); H01L 29/08 (2006.01); H01L 29/49 (2006.01); H01L 29/78 (2006.01)
CPC H01L 29/4983 (2013.01) [H01L 21/823431 (2013.01); H01L 21/823468 (2013.01); H01L 21/823821 (2013.01); H01L 21/823864 (2013.01); H01L 27/0886 (2013.01); H01L 29/0847 (2013.01); H01L 29/6653 (2013.01); H01L 29/66545 (2013.01); H01L 29/6656 (2013.01); H01L 29/66636 (2013.01); H01L 29/66795 (2013.01); H01L 29/785 (2013.01); H01L 29/7851 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method, comprising:
forming a fin structure with a fin top surface on a substrate;
forming first and second polysilicon structures on the fin top surface;
forming a spacer opening in the fin structure and between the first and second polysilicon structures;
forming a gate spacer, wherein forming the gate spacer comprises:
forming a first spacer portion of the gate spacer along a sidewall of the first polysilicon structure, and
forming a second spacer portion of the gate spacer, in the spacer opening, comprising forming the second spacer portion with a triangular-shaped structure comprising a first sloped spacer sidewall facing the fin structure and a second sloped spacer sidewall facing the spacer opening;
forming a source/drain (S/D) region, between the first and second polysilicon structures, comprising forming the S/D region with a sloped sidewall adjacent to the second sloped spacer sidewall; and
replacing the first and second polysilicon structures with first and second gate structures.
 
10. A method, comprising:
forming first and second fin structures on a substrate;
forming first and second polysilicon structures on the first and second fin structures, respectively;
forming a first gate spacer comprising a first spacer portion along a sidewall of the first polysilicon structure and a second spacer portion along a fin sidewall of the first fin structure;
forming, at a same time as forming the first gate spacer, a second gate spacer comprising a third spacer portion along a sidewall of the second polysilicon structure and a fourth spacer portion along a fin sidewall of the second fin structure, wherein a height of the second spacer portion is greater than a height of the fourth spacer portion;
forming a first source/drain (S/D) region adjacent to the first gate spacer;
forming a second S/D region adjacent to the second gate spacer; and
replacing the first and second polysilicon structures with first and second gate structures.
 
16. A method, comprising:
forming a fin structure on a substrate;
forming a spacer opening, in the fin structure, comprising etching the fin structure with a fluorine-based etching gas in a gas mixture comprising chlorine, hydrogen bromide, and helium, wherein a ratio of the fluorine-based etching gas to the gas mixture is about 1:10 to about 1:25;
forming a spacer along a sidewall of the fin structure and in the spacer opening; and
forming a source/drain (S/D) region comprising a first S/D portion along a sidewall of the spacer and a second S/D portion along a sidewall of the fin structure, wherein entire sidewalls of the second S/D portion are substantially vertical.