US 12,218,215 B2
Semiconductor device and method of manufacturing semiconductor device
Shunsuke Asaba, Himeji Hyogo (JP); Yuji Kusumoto, Tatsuno Hyogo (JP); Katsuhisa Tanaka, Himeji Hyogo (JP); Yujiro Hara, Himeji Hyogo (JP); Makoto Mizukami, Ibo Hyogo (JP); Masaru Furukawa, Himeji Hyogo (JP); Hiroshi Kono, Himeji Hyogo (JP); and Masanori Nagata, Himeji Hyogo (JP)
Assigned to Toshiba Electronic Devices & Storage Corporation, Tokyo (JP); and Kabushiki Kaisha Toshiba, Tokyo (JP)
Filed by TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION, Tokyo (JP); and KABUSHIKI KAISHA TOSHIBA, Tokyo (JP)
Filed on Feb. 25, 2022, as Appl. No. 17/681,410.
Claims priority of application No. 2021-154470 (JP), filed on Sep. 22, 2021.
Prior Publication US 2023/0086599 A1, Mar. 23, 2023
Int. Cl. H01L 29/45 (2006.01); H01L 21/04 (2006.01); H01L 29/10 (2006.01); H01L 29/16 (2006.01); H01L 29/66 (2006.01); H01L 29/78 (2006.01)
CPC H01L 29/45 (2013.01) [H01L 21/0465 (2013.01); H01L 21/0485 (2013.01); H01L 29/1095 (2013.01); H01L 29/1608 (2013.01); H01L 29/66068 (2013.01); H01L 29/7802 (2013.01)] 17 Claims
OG exemplary drawing
 
1. A semiconductor device, comprising:
a silicon carbide layer having a first face and a second face spaced from the first face, the silicon carbide layer including:
a first silicon carbide region of a first conductivity type having a first region in contact with the first face,
a second silicon carbide region of a second conductivity type between the first silicon carbide region and the first face and having a second region in contact with the first face,
a third silicon carbide region of the second conductivity type between the second silicon carbide region and the first face and having a second conductivity type impurity concentration that is higher than a second conductivity type impurity concentration of the second silicon carbide region,
a fourth silicon carbide region of the first conductivity type between the third silicon carbide region and the first face and in contact with the first face, and
a fifth silicon carbide region of the first conductivity type between the third silicon carbide region and the first face and in contact with the first face, the fifth silicon carbide region being in a first direction from the fourth silicon carbide region, the first direction parallel to the first face;
a gate electrode on a first face side of the silicon carbide layer, the gate electrode facing the first region and the second region;
a gate insulating layer between the first region and the gate electrode and between the second region and the gate electrode;
a first electrode on the first face side of the silicon carbide layer and including a first portion between the fourth silicon carbide region and the fifth silicon carbide region in the first direction;
a second electrode on a second face side of the silicon carbide layer; and
a metal silicide layer between the first portion and the third silicon carbide region and in contact with the third silicon carbide region, the metal silicide layer being between the first portion and the fourth silicon carbide region and in contact with the fourth silicon carbide region, and between the first portion and the fifth silicon carbide region and in contact with the fifth silicon carbide region.