US 12,218,211 B2
Structures of gate contact formation for vertical transistors
Sang-Yun Lee, Portland, OR (US)
Assigned to BESANG, INC., Hillsboro, OR (US)
Filed by Sang-Yun Lee
Filed on Aug. 11, 2023, as Appl. No. 18/233,293.
Application 18/233,293 is a division of application No. 17/083,026, filed on Oct. 28, 2020, granted, now 11,769,809.
Prior Publication US 2024/0021689 A1, Jan. 18, 2024
Int. Cl. H01L 29/423 (2006.01); H01L 25/18 (2023.01); H01L 29/06 (2006.01); H01L 29/40 (2006.01); H01L 29/66 (2006.01); H01L 29/78 (2006.01); H01L 29/792 (2006.01); H10B 12/00 (2023.01); H10B 43/27 (2023.01); H10B 43/35 (2023.01); H10B 43/40 (2023.01)
CPC H01L 29/4234 (2013.01) [H01L 25/18 (2013.01); H01L 29/0649 (2013.01); H01L 29/401 (2013.01); H01L 29/66666 (2013.01); H01L 29/66833 (2013.01); H01L 29/7827 (2013.01); H01L 29/7926 (2013.01); H10B 12/05 (2023.02); H10B 12/31 (2023.02); H10B 12/50 (2023.02); H10B 43/27 (2023.02); H10B 43/35 (2023.02); H10B 43/40 (2023.02)] 17 Claims
OG exemplary drawing
 
1. A modified vertical transistor comprising:
a semiconductor pillar standing over a substrate;
a gate dielectric disposed over at least a portion of said semiconductor pillar;
a gate surrounding a middle portion of said semiconductor pillar over said gate dielectric;
an extended gate region disposed over a top of said semiconductor pillar and extending upward from said gate;
and wherein said semiconductor pillar comprises:
a first region of a first doping type in said middle portion of said semiconductor pillar;
a second region of a second doping type occupying a top portion of said semiconductor pillar, extending partly into said middle portion from said top portion, and contiguous with said first region; and
a third region of said second doping type occupying a bottom portion of said semiconductor pillar, extending partly into said middle portion from said bottom portion, and contiguous with said first region.