US 12,218,209 B2
Contacts for semiconductor devices and methods of forming the same
Meng-Han Lin, Hsinchu (TW); Sai-Hooi Yeong, Zhubei (TW); and Chi On Chui, Hsinchu (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed on Nov. 22, 2023, as Appl. No. 18/517,458.
Application 18/517,458 is a continuation of application No. 17/814,325, filed on Jul. 22, 2022, granted, now 11,855,162.
Application 17/814,325 is a continuation of application No. 17/146,205, filed on Jan. 11, 2021, granted, now 11,417,739, issued on Aug. 16, 2022.
Claims priority of provisional application 63/090,799, filed on Oct. 13, 2020.
Prior Publication US 2024/0088244 A1, Mar. 14, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 29/417 (2006.01); H01L 21/8234 (2006.01); H01L 21/8238 (2006.01); H01L 27/088 (2006.01); H01L 27/092 (2006.01); H01L 29/10 (2006.01); H01L 29/40 (2006.01); H01L 29/423 (2006.01); H01L 29/51 (2006.01); H01L 29/66 (2006.01)
CPC H01L 29/41775 (2013.01) [H01L 21/823456 (2013.01); H01L 21/823462 (2013.01); H01L 21/823475 (2013.01); H01L 21/823857 (2013.01); H01L 21/823871 (2013.01); H01L 27/088 (2013.01); H01L 27/0922 (2013.01); H01L 29/1079 (2013.01); H01L 29/401 (2013.01); H01L 29/42364 (2013.01); H01L 29/513 (2013.01); H01L 29/66545 (2013.01); H01L 29/66606 (2013.01); H01L 29/66621 (2013.01)] 20 Claims
OG exemplary drawing
 
8. A semiconductor device comprising:
a first transistor comprising:
a first gate stack over a semiconductor substrate, the first gate stack having a first gate dielectric, the first gate dielectric having a first thickness;
a first source/drain region adjacent the first gate stack; and
a first source/drain contact electrically coupled to the first source/drain region, a top surface of the first source/drain contact having a first width; and
a second transistor comprising:
a second gate stack over the semiconductor substrate, the second gate stack having a second gate dielectric, the second gate dielectric having a second thickness less than the first thickness, wherein an upper surface of the first gate stack is level with an upper surface of the second gate stack;
a second source/drain region adjacent the second gate stack; and
a second source/drain contact electrically coupled to the second source/drain region, a top surface of the second source/drain contact having a second width less than the first width.