US 12,218,206 B2
Power semiconductor device and method of manufacturing the same
Sunkyu Hwang, Seoul (KR); and Jongseob Kim, Seoul (KR)
Assigned to Samsung Electronics Co., Ltd., Gyeonggi-do (KR)
Filed by Samsung Electronics Co., Ltd., Suwon-si (KR)
Filed on Mar. 3, 2022, as Appl. No. 17/685,886.
Claims priority of application No. 10-2021-0041267 (KR), filed on Mar. 30, 2021; and application No. 10-2021-0054645 (KR), filed on Apr. 27, 2021.
Prior Publication US 2022/0320297 A1, Oct. 6, 2022
Int. Cl. H01L 29/08 (2006.01); H01L 29/20 (2006.01); H01L 29/40 (2006.01); H01L 29/66 (2006.01); H01L 29/778 (2006.01)
CPC H01L 29/401 (2013.01) [H01L 29/2003 (2013.01); H01L 29/66462 (2013.01); H01L 29/7787 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method of manufacturing a power semiconductor device, the method comprising:
forming a channel separation pattern on a substrate;
forming a passivation layer on the substrate and the channel separation pattern; and
forming a gate electrode pattern, a source electrode pattern, and a drain electrode pattern penetrating the passivation layer in a same process step,
wherein the gate electrode pattern is formed on the channel separation pattern, and
a side surface of the gate electrode pattern and a side surface of the channel separation pattern have a step difference.