US 12,218,205 B2
2D-channel transistor structure with source-drain engineering
Dhanyakumar Mahaveer Sathaiya, Hsinchu (TW); Khaderbad Mrunal Abhijith, Hsinchu (TW); and Tzer-Min Shen, Hsinchu (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsin-Chu (TW)
Filed on Jul. 19, 2023, as Appl. No. 18/354,820.
Application 18/354,820 is a continuation of application No. 17/218,212, filed on Mar. 31, 2021, granted, now 11,728,391.
Claims priority of provisional application 63/062,840, filed on Aug. 7, 2020.
Prior Publication US 2023/0361180 A1, Nov. 9, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 29/24 (2006.01); H01L 29/16 (2006.01); H01L 29/267 (2006.01); H01L 29/66 (2006.01); H01L 29/78 (2006.01)
CPC H01L 29/24 (2013.01) [H01L 29/1606 (2013.01); H01L 29/267 (2013.01); H01L 29/66545 (2013.01); H01L 29/66636 (2013.01); H01L 29/66795 (2013.01); H01L 29/7851 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor device, comprising:
a channel member including a first channel layer and a second channel layer over the first channel layer;
a dielectric feature inserted between the second channel layer and the first channel layer;
a gate structure over the channel member; and
a source feature and a drain feature of a semiconductor material,
wherein the second channel layer includes a two-dimensional material, and wherein the semiconductor material of the source and drain features electrically connects to the first and second channel layers.