US 12,218,200 B2
Semiconductor device and method
Hsin-Yi Lee, Hsinchu (TW); Cheng-Lung Hung, Hsinchu (TW); and Chi On Chui, Hsinchu (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed on Jul. 26, 2023, as Appl. No. 18/359,695.
Application 18/359,695 is a continuation of application No. 17/317,519, filed on May 11, 2021, granted, now 11,810,948.
Claims priority of provisional application 63/158,987, filed on Mar. 10, 2021.
Prior Publication US 2023/0387202 A1, Nov. 30, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 29/06 (2006.01); H01L 27/092 (2006.01)
CPC H01L 29/0673 (2013.01) [H01L 27/0924 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method comprising:
forming a first nanostructure and a second nanostructure over a substrate, the second nanostructure being over the first nanostructure, the first nanostructure comprising a first channel region, the second nanostructure comprising a second channel region;
forming a first gate dielectric layer on the first channel region and the second channel region;
forming a first work function tuning layer on the first gate dielectric layer, the first work function tuning layer extending from the first gate dielectric layer on the first channel region to the first gate dielectric layer on the second channel region, the first work function tuning layer comprising a first n-type work function metal, aluminum, and carbon, wherein the first n-type work function metal comprises zirconium;
forming a first barrier layer on the first work function tuning layer;
forming a glue layer on the first barrier layer; and
forming a fill layer on the glue layer.