US 12,218,199 B2
Transistor gate structures and methods of forming the same
Hsin-Yi Lee, Hsinchu (TW); Jia-Ming Lin, Hsinchu (TW); and Chi On Chui, Hsinchu (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed on Jun. 13, 2023, as Appl. No. 18/333,981.
Application 18/333,981 is a continuation of application No. 17/220,335, filed on Apr. 1, 2021, granted, now 11,715,762.
Claims priority of provisional application 63/142,557, filed on Jan. 28, 2021.
Prior Publication US 2023/0326967 A1, Oct. 12, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 29/06 (2006.01); H01L 21/265 (2006.01); H01L 27/092 (2006.01)
CPC H01L 29/0673 (2013.01) [H01L 21/2654 (2013.01); H01L 27/0924 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A device comprising:
a first nanostructure;
a second nanostructure;
a gate dielectric around the first nanostructure and the second nanostructure; and
a gate electrode comprising:
a work function tuning layer on the gate dielectric, the work function tuning layer and the gate dielectric completely filling a region between the first nanostructure and the second nanostructure, the work function tuning layer comprising a multi-layer of pure work function metals, an upper one of the pure work function metals having a different thickness than a lower one of the pure work function metals;
an adhesion layer on the work function tuning layer; and
a fill layer on the adhesion layer.