CPC H01L 29/0673 (2013.01) [H01L 21/02164 (2013.01); H01L 21/0217 (2013.01); H01L 21/02178 (2013.01); H01L 21/02181 (2013.01); H01L 29/0847 (2013.01); H01L 29/66545 (2013.01); H01L 29/66795 (2013.01); H01L 29/785 (2013.01)] | 20 Claims |
1. A method of forming a source/drain region of a gate-all-around field effect transistor (GAA FET), the method comprising:
forming a first support layer;
forming a first dielectric layer over the first support layer;
disposing carbon nanotubes (CNTs) over the first dielectric layer;
forming a second dielectric layer to fully cover the CNTs;
removing a part of the second dielectric layer to partially expose the CNTs, such that, within a cross-section perpendicular to an axial direction, each CNT is partially enclosed by the second dielectric layer;
forming a second support layer over the second dielectric layer to form a stacked layer such that, within the cross-section perpendicular to the axial direction, each CNT is in contact with the second dielectric layer and the second support layer;
patterning the stacked layer to form fin structures;
removing the first support layer and the second support layer from the patterned stacked layer; and
forming a source/drain contact layer to contact the exposed CNTs,
wherein the source/drain contact is formed such that, within the cross-section perpendicular to the axial direction, the source/drain contact is in direct contact with only a part of each of the CNTs, and a part of the first or second dielectric layers is disposed between the source/drain contact and the CNTs.
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