| CPC H01L 29/0665 (2013.01) [H01L 21/823412 (2013.01); H01L 21/823418 (2013.01); H01L 21/823468 (2013.01); H01L 29/42392 (2013.01); H01L 29/66545 (2013.01); H01L 29/66742 (2013.01); H01L 29/78618 (2013.01); H01L 29/78696 (2013.01)] | 20 Claims |

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1. A method comprising:
depositing a multi-layer stack on a semiconductor substrate, the multi-layer stack comprising a plurality of sacrificial layers that alternate with a plurality of channel layers;
forming a dummy gate on the multi-layer stack;
forming a first spacer on a sidewall of the dummy gate;
performing a first implantation process to form a first doped region, the first implantation process having a first implant energy and a first implant dose;
performing a second implantation process to form a second doped region, wherein the first doped region and the second doped region are in a portion of the channel layers uncovered by the first spacer and the dummy gate, the second implantation process having a second implant energy and a second implant dose, wherein the second implant energy is greater than the first implant energy, and wherein the first implant dose is different from the second implant dose;
after performing the first implantation process and the second implantation process, forming a second spacer on a sidewall of the first spacer;
forming a first recess in the multi-layer stack adjacent the second spacer; and
forming an epitaxial source/drain region in the first recess.
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