US 12,218,194 B2
Semiconductor device and method for fabricating the same
Hae Jung Park, Gyeonggi-do (KR)
Assigned to SK hynix Inc., Gyeonggi-do (KR)
Filed by SK hynix Inc., Gyeonggi-do (KR)
Filed on Nov. 1, 2022, as Appl. No. 17/978,390.
Application 17/978,390 is a continuation of application No. 17/173,539, filed on Feb. 11, 2021, granted, now 11,515,389.
Claims priority of application No. 10-2020-0117593 (KR), filed on Sep. 14, 2020.
Prior Publication US 2023/0059787 A1, Feb. 23, 2023
Int. Cl. H01L 29/06 (2006.01); H01L 21/285 (2006.01); H01L 21/768 (2006.01); H01L 29/423 (2006.01); H01L 29/49 (2006.01); H01L 29/78 (2006.01)
CPC H01L 29/0653 (2013.01) [H01L 21/28525 (2013.01); H01L 21/76831 (2013.01); H01L 21/76879 (2013.01); H01L 29/42356 (2013.01); H01L 29/49 (2013.01); H01L 29/7813 (2013.01)] 11 Claims
OG exemplary drawing
 
1. A method for fabricating a semiconductor device, comprising:
providing a substrate including a plurality of active regions;
forming a plurality of bit line structures in which bit line contact plugs, bit lines, and bit line hard masks are stacked over the substrate;
forming an isolation layer filling a space between the bit line structures and having an opening exposing the active regions between the bit line structures;
forming a pad in a bottom portion of the opening;
forming plug liner over a sidewall of the opening and exposing the pad; and
forming a contact plug filling the opening over the pad,
wherein the upper surface of the pad is positioned at a lower level than the upper surface of the each bit line contact plug,
wherein the plug liner includes polysilicon.