US 12,218,190 B2
False collectors and guard rings for semiconductor devices
Alexei Sadovnikov, Sunnyvale, CA (US); and Guruvayurappan S. Mathur, Allen, TX (US)
Assigned to TEXAS INSTRUMENTS INCORPORATED, Dallas, TX (US)
Filed by TEXAS INSTRUMENTS INCORPORATED, Dallas, TX (US)
Filed on Apr. 28, 2022, as Appl. No. 17/731,510.
Application 17/731,510 is a continuation in part of application No. 17/710,320, filed on Mar. 31, 2022, granted, now 12,015,054.
Prior Publication US 2023/0317775 A1, Oct. 5, 2023
Int. Cl. H01L 29/06 (2006.01); H01L 21/762 (2006.01); H01L 29/78 (2006.01)
CPC H01L 29/0623 (2013.01) [H01L 21/76202 (2013.01); H01L 21/76232 (2013.01); H01L 29/063 (2013.01); H01L 29/7823 (2013.01)] 23 Claims
OG exemplary drawing
 
1. A method of manufacturing an integrated circuit, the method comprising:
forming first and second false collector regions of a first conductivity type adjacent to a surface of an epitaxial layer of semiconductor material,
the first false collector region being located laterally on a first side of a base region, the base region formed within the epitaxial layer and having a second conductivity type,
the second false collector region being located laterally on a second side of the base region, the second side being opposite the first side of the base region, and
the base region being a base of a parasitic bipolar junction in an isolation region of a semiconductor device.