US 12,218,183 B2
Method for manufacturing semiconductor structure and semiconductor structure
Yulei Wu, Hefei (CN)
Assigned to CHANGXIN MEMORY TECHNOLOGIES, INC., Hefei (CN)
Filed by CHANGXIN MEMORY TECHNOLOGIES, INC., Hefei (CN)
Filed on Jan. 11, 2022, as Appl. No. 17/647,614.
Application 17/647,614 is a continuation of application No. PCT/CN2021/106440, filed on Jul. 15, 2021.
Claims priority of application No. 202110753737.0 (CN), filed on Jul. 2, 2021.
Prior Publication US 2023/0006032 A1, Jan. 5, 2023
Int. Cl. H10B 12/00 (2023.01); H01L 49/02 (2006.01)
CPC H01L 28/75 (2013.01) [H01L 28/91 (2013.01); H10B 12/033 (2023.02); H10B 12/315 (2023.02); H10B 12/318 (2023.02)] 12 Claims
OG exemplary drawing
 
1. A method for manufacturing a semiconductor structure, comprising:
forming a plurality of capacitor holes on a substrate, and exposing a part of the substrate on bottoms of the capacitor holes;
forming a bottom electrode layer on surfaces of the capacitor holes;
forming a dielectric layer continuously covering a surface of the bottom electrode layer;
forming a first top electrode layer to continuously cover a surface of the dielectric layer by a first film forming process, a material of the first top electrode layer comprises TiN; and
by a second film forming process, forming, in a circumferential direction of the capacitor holes, a second top electrode layer continuously covering a surface of the first top electrode layer, and forming, in an axial direction of the capacitor holes, a second top electrode layer discontinuously covering the surface of the first top electrode layer,
wherein a material of the second top electrode layer comprises TIN, wherein the first film forming process comprises a first deposition rate, the second film forming process comprises a second deposition rate, and the first deposition rate is less than the second deposition rate.