US 12,218,171 B2
Low-noise image sensor having stacked semiconductor substrates
Seiji Takahashi, Hsinchu (TW); and Jhy-Jyi Sze, Hsin-Chu (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu (TW)
Filed on Jun. 30, 2022, as Appl. No. 17/854,590.
Application 17/854,590 is a division of application No. 16/526,030, filed on Jul. 30, 2019, granted, now 11,482,556.
Claims priority of provisional application 62/806,455, filed on Feb. 15, 2019.
Prior Publication US 2022/0336515 A1, Oct. 20, 2022
Int. Cl. H01L 27/146 (2006.01)
CPC H01L 27/14636 (2013.01) [H01L 27/14603 (2013.01); H01L 27/14612 (2013.01); H01L 27/14616 (2013.01); H01L 27/14634 (2013.01); H01L 27/14641 (2013.01); H01L 27/14689 (2013.01); H01L 27/1469 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method for forming an image sensor, the method comprising:
forming a plurality of photodetectors in a first semiconductor substrate;
forming a plurality of floating diffusion nodes in the first semiconductor substrate, wherein the plurality of floating diffusion nodes respectively correspond to the plurality of photodetectors;
forming a first interlayer dielectric (ILD) structure over the first semiconductor substrate;
bonding a second semiconductor substrate to the first semiconductor substrate, such that the first ILD structure is disposed vertically between the second semiconductor substrate and the first semiconductor substrate;
forming a first isolation structure in the second semiconductor substrate;
forming a gate electrode of a readout transistor over the second semiconductor substrate, the first ILD structure, and the first semiconductor substrate;
forming a pair of source/drain (S/D) regions of the readout transistor in the second semiconductor substrate, wherein the S/D regions of the pair of S/D regions are formed on opposite sides of the gate electrode;
after the first isolation structure is formed, forming a second ILD structure over the first isolation structure, the second semiconductor substrate, the gate electrode, the first ILD structure, and the first semiconductor substrate;
forming a plurality of floating diffusion node contacts (FDNCs) overlying the plurality of floating diffusion nodes, respectively, wherein the plurality of FDNCs are formed extending vertically from the plurality of floating diffusion nodes, respectively, and wherein the plurality of FDNCs are formed in the second ILD structure, the first isolation structure, and the first ILD structure;
forming a S/D contact overlying a first S/D region of the pair of S/D regions, wherein the S/D contact is formed extending vertically from the first S/D region, and wherein the S/D contact is formed in the second ILD structure;
forming a third ILD structure over the second ILD structure, the plurality of FDNCs, and the S/D contact; and
forming a conductive line in the third ILD structure, wherein the conductive line is formed overlying the plurality of FDNCs and overlying the S/D contact, and wherein the conductive line is formed electrically coupled to the plurality of FDNCs and electrically coupled to the S/D contact.