US 12,218,167 B2
Solid-state imaging device and electronic device
Kentaro Akiyama, Kanagawa (JP); and Junichiro Fujimagari, Kanagawa (JP)
Assigned to SONY SEMICONDUCTOR SOLUTIONS CORPORATION, Kanagawa (JP)
Appl. No. 17/281,452
Filed by SONY SEMICONDUCTOR SOLUTIONS CORPORATION, Kanagawa (JP)
PCT Filed Aug. 16, 2019, PCT No. PCT/JP2019/032182
§ 371(c)(1), (2) Date Mar. 30, 2021,
PCT Pub. No. WO2020/075388, PCT Pub. Date Apr. 16, 2020.
Claims priority of application No. 2018-192451 (JP), filed on Oct. 11, 2018.
Prior Publication US 2021/0408097 A1, Dec. 30, 2021
Int. Cl. H01L 27/146 (2006.01)
CPC H01L 27/14636 (2013.01) [H01L 27/14634 (2013.01); H01L 27/1469 (2013.01)] 11 Claims
OG exemplary drawing
 
1. A solid-state imaging device, comprising:
a first semiconductor element that includes:
a first semiconductor layer that includes:
a first through via; and
a photoelectric conversion unit in a region of the first semiconductor layer, wherein the photoelectric conversion unit is configured to photoelectrically convert light incident on a light incident surface side of the first semiconductor layer;
a connection part that is wider than the first through via, wherein
the connection part is outside the region of the first semiconductor layer that includes the photoelectric conversion unit,
the connection part includes a first metal layer and a second metal layer different from the first metal layer, and
the second metal layer is on the first metal layer;
a connection wiring on the first semiconductor layer, wherein the connection wiring connects the first through via and the connection part; and
a first passivation layer on the light incident surface side, wherein the first metal layer and the second metal layer are between the first passivation layer and the first semiconductor layer;
a second semiconductor element on the first semiconductor element, wherein the connection part is between the first semiconductor element and the second semiconductor element;
a second semiconductor layer;
a second passivation layer;
a first guard ring on an outer peripheral portion of the first semiconductor element, wherein
the first guard ring surrounds the first semiconductor element,
at least a part of the first guard ring is outside the first semiconductor layer and above the second semiconductor layer, and
the first guard ring is outside the first passivation layer and below the second passivation layer; and
a plurality of third guard rings below the second semiconductor layer, wherein
at least a first of the plurality of third guard rings is connected in series to the first guard ring, and
at least a second of the plurality of third guard rings is connected to the second semiconductor layer.