US 12,218,160 B2
Pixel sensor including a layer stack to reduce and/or block the effects of plasma processing and etching on the pixel sensor
Wei-Lin Chen, Tainan (TW); Ching-Chung Su, Tainan (TW); Chun-Hao Chou, Tainan (TW); and Kuo-Cheng Lee, Tainan (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on Mar. 12, 2021, as Appl. No. 17/249,788.
Prior Publication US 2022/0293651 A1, Sep. 15, 2022
Int. Cl. H01L 27/146 (2006.01)
CPC H01L 27/14618 (2013.01) [H01L 27/14621 (2013.01); H01L 27/14627 (2013.01); H01L 27/14685 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method, comprising:
forming a plurality of photodiodes in a substrate of a pixel array,
wherein each of the plurality of photodiodes is associated with a respective pixel sensor included in the pixel array;
forming a first oxide layer over the plurality of photodiodes;
forming a silicon nitride layer directly on the first oxide layer,
wherein a band gap of the silicon nitride layer is lower than a band gap of the first oxide layer;
forming a second oxide layer directly on the silicon nitride layer;
forming a grid structure over the second oxide layer;
forming a passivation liner over a top layer of the grid structure, on sidewalls of the grid structure, and on a portion of the second oxide layer;
removing a first portion of the passivation liner from the second oxide layer;
forming a plurality of color filter regions in between portions of the passivation liner on the sidewalls of the grid structure and directly on a surface of the second oxide layer; and
forming a micro-lens layer over a second portion of the passivation liner and over the plurality of color filter regions,
wherein the second portion of the passivation liner is over an entire portion of the top layer of the grid structure.