US 12,218,157 B2
Optical receiver comprising monolithically integrated photodiode and transimpedance amplifier
Lawrence E. Tarof, Kanata (CA); William A. Hagley, Ottawa (CA); Gudmundur A. Hjartarson, Ottawa (CA); and John William Mitchell Rogers, Nepean (CA)
Assigned to ElectroPhotonic-IC Inc., Kanata (CA)
Appl. No. 17/785,989
Filed by ElectroPhotonic-IC Inc., Kanata (CA)
PCT Filed Dec. 4, 2020, PCT No. PCT/CA2020/051666
§ 371(c)(1), (2) Date Jun. 16, 2022,
PCT Pub. No. WO2021/119803, PCT Pub. Date Jun. 24, 2021.
Claims priority of provisional application 62/950,479, filed on Dec. 19, 2019.
Prior Publication US 2023/0019783 A1, Jan. 19, 2023
Int. Cl. H01L 27/144 (2006.01); H04B 10/60 (2013.01)
CPC H01L 27/1443 (2013.01) [H04B 10/60 (2013.01)] 32 Claims
OG exemplary drawing
 
1. An optical receiver comprising a monolithically integrated photodiode (PD) and transimpedance amplifier (TIA), wherein:
an epitaxial layer stack is formed on a semi-insulating indium phosphide (SI:InP) substrate;
the TIA comprises InP heterojunction bipolar transistors (HBT) formed by a first plurality of semiconductor layers of the epitaxial layer stack formed on the SI:InP substrate;
the PD comprises a p-i-n diode (PIN) formed by a second plurality of semiconductor layers of the epitaxial layer stack, comprising an n-layer, an i-layer and a p-layer, the second plurality of semiconductor layers being formed on top of the first plurality of semiconductor layers of the epitaxial layer stack;
a p-contact of the PIN is directly interconnected by a conductive trace to an input of the TIA, to provide a device capacitance CPIN of the PIN, and a capacitance CTIA of the TIA; and
device parameters comprising values of: CPIN, CTIA, a thickness ti of the i-layer, an area of the PIN; and a transimpedance feedback resistance RF of the TIA are selected to provide an integrated PIN-TIA meeting performance specifications comprising a specified sensitivity and responsivity at an operational wavelength.