US 12,218,156 B2
Display device having power line electrically connected to electrode layers located above and below transistor
Youngin Hwang, Yongin-si (KR); Elly Gil, Yongin-si (KR); Sungho Kim, Yongin-si (KR); Eungtaek Kim, Yongin-si (KR); Yongho Yang, Yongin-si (KR); Seongmin Wang, Yongin-si (KR); Jina Lee, Yongin-si (KR); Joohyeon Jo, Yongin-si (KR); and Seongbaik Chu, Yongin-si (KR)
Assigned to SAMSUNG DISPLAY CO., LTD., Yongin-si (KR)
Filed by Samsung Display Co., Ltd., Yongin-si (KR)
Filed on Nov. 10, 2023, as Appl. No. 18/388,594.
Application 18/388,594 is a continuation of application No. 17/099,629, filed on Nov. 16, 2020, granted, now 11,855,104.
Application 17/099,629 is a continuation of application No. 16/361,135, filed on Mar. 21, 2019, granted, now 10,903,250, issued on Jan. 26, 2021.
Claims priority of application No. 10-2018-0075937 (KR), filed on Jun. 29, 2018.
Prior Publication US 2024/0079419 A1, Mar. 7, 2024
Int. Cl. H01L 27/14 (2006.01); G09G 3/3225 (2016.01); H01L 27/12 (2006.01); H10K 59/121 (2023.01); H10K 59/131 (2023.01)
CPC H01L 27/1255 (2013.01) [G09G 3/3225 (2013.01); H01L 27/1222 (2013.01); H01L 27/124 (2013.01); H10K 59/1213 (2023.02); H10K 59/1216 (2023.02); H10K 59/131 (2023.02)] 20 Claims
OG exemplary drawing
 
1. A display device comprising:
a bottom metal layer;
a semiconductor layer disposed on the bottom metal layer;
a first electrode layer disposed on the semiconductor layer;
a second electrode layer disposed on the first electrode layer and overlapping the first electrode layer;
a power line disposed on the second electrode layer and electrically connected to the bottom metal layer and the second electrode layer; and
a light-emitting device comprising a pixel electrode, a common electrode facing the pixel electrode, and an emission layer between the pixel electrode and the common electrode,
wherein a first end of the semiconductor layer is electrically connected to the power line and a second end of the semiconductor layer is electrically connected to the pixel electrode,
wherein the semiconductor layer comprises a source area, a drain area, and a channel area between the source area and the drain area,
wherein each of the bottom metal layer, the first electrode layer, the second electrode layer, and the power line overlaps the channel area of the semiconductor layer, and
wherein the channel area of the semiconductor layer is located between a connected part of the power line and the first end of the semiconductor layer and a connected part of the second end of the semiconductor layer and the pixel electrode.