CPC H01L 27/1248 (2013.01) [G02F 1/133357 (2021.01); H01L 24/06 (2013.01); G02F 1/133784 (2013.01); G02F 1/13456 (2021.01); G02F 1/136222 (2021.01); H01L 23/544 (2013.01); H01L 2223/54433 (2013.01); H01L 2224/06165 (2013.01); H01L 2224/06515 (2013.01)] | 16 Claims |
1. An array substrate, comprising a display region and a binding region located at a side of the display region, wherein
the binding region comprises a first conductive layer disposed on the substrate and a planarization layer disposed at a side of the first conductive layer away from the substrate;
the binding region comprises a binding zone and a vacancy zone alternately disposed along an edge of the display region;
the first conductive layer comprises a plurality of binding pins disposed in the binding zone; and
the planarization layer is provided with first openings exposing the plurality of binding pins and covering the binding zone and the vacancy zone;
wherein the first conductive layer further comprises occupation pins disposed in the vacancy zone, and the occupation pins and the binding pins are disposed at intervals along the edge of the display region;
wherein distances between the adjacent binding pins, between the adjacent occupation pins and between the adjacent occupation pin and the binding pin are the same.
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