US 12,218,141 B2
Hybrid fin field-effect transistor cell structures and related methods
Wei-An Lai, Taichung (TW); Hui-Zhong Zhuang, Kaohsiung (TW); Jiann-Tyng Tzeng, Hsin Chu (TW); Wei-Cheng Lin, Taichung (TW); Lipen Yuan, Hsinchu County (TW); and Yan-Hao Chen, Hsinchu (TW)
Assigned to Taiwan Semiconductor Manufacturing Company Limited, Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company Limited, Hsinchu (TW)
Filed on Sep. 24, 2020, as Appl. No. 17/030,550.
Application 17/030,550 is a continuation of application No. 16/102,803, filed on Aug. 14, 2018, granted, now 10,797,078.
Prior Publication US 2021/0005633 A1, Jan. 7, 2021
Int. Cl. H01L 27/02 (2006.01); H01L 27/12 (2006.01); H01L 29/417 (2006.01); H01L 29/66 (2006.01); H01L 29/78 (2006.01)
CPC H01L 27/1211 (2013.01) [H01L 27/0207 (2013.01); H01L 29/41791 (2013.01); H01L 29/66795 (2013.01); H01L 29/785 (2013.01)] 20 Claims
OG exemplary drawing
 
10. A circuit cell for a flip-flop, comprising:
a first stage configured to receive a flip-flop input and pass the flip-flop input through to a first stage output in response to a signal, the first stage including field-effect transistors (finFETs) formed in one of a first fin portion of the circuit cell or a second fin portion of the circuit cell based on a performance optimization criterion, wherein the first fin portion of the circuit cell includes a first plurality of fin structures arranged in a plurality of first rows, and the second fin portion of the circuit cell includes a second plurality of fin structures arranged in a plurality of second rows, wherein each of the second rows, in the second fin portion, contain a lesser number of fin structures than each of the first rows, in the first fin portion of the circuit cell;
a second stage connected to the first stage and configured to receive the first stage output and generate a first latched output in response to the signal, the second stage including finFETs in a forward path that are formed in the first fin portion of the circuit cell and finFETs in a feedback path that are formed in the second fin portion of the circuit cell; and
a third stage configured to generate a second stage output and including finFETs formed in the first fin portion, the second fin portion, or the first and second fin portions.